electronic design automation

5 papers

• Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithms
• CORE: Collaborative Optimization with Reinforcement Learning and Evolutionary Algorithm for Floorplanning
• Functional Matching of Logic Subgraphs: Beyond Structural Isomorphism
• MIHC: Multi-View Interpretable Hypergraph Neural Networks with Information Bottleneck for Chip Congestion Prediction
• QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation